Metal-oxide-semiconductor (MOS) transistors are basic devices of semiconductor manufacturing processes, and have been widely used in all types of integrated circuits (ICs). MOS transistors can be categorized into NMOS transistors and PMOS based on types of carriers and dopants used in the manufacturing processes.
FIGS. 1-4 illustrate semiconductor structures corresponding to certain stages of an existing fabrication process for forming a MOS transistor.
As shown in FIG. 1, a semiconductor substrate 100 is provided, and a gate structure having a gate dielectric layer 102 and a gate electrode 103 is sequentially formed on the semiconductor substrate 100. The process also includes forming an offset sidewall spacer 104 on surfaces of both sides of the gate structure, and forming shallow trench isolation structures 101 in the semiconductor substrate 100.
Further, as shown in FIG. 2, lightly doped regions 105 are formed in the semiconductor substrate 100 at both sides of the gate structure by a lightly doped ion implantation process using the gate structure and the offset sidewall spacer 104 as a mask. As shown in FIG. 3, a main sidewall spacer 111 is formed on a surface of the offset sidewall spacer 104, heavily doped regions 112 are formed in the semiconductor substrate 100 at both sides of the gate structure and the main sidewall spacer 111 by a source/drain ion implantation process using the gate structure and the main sidewall spacer 111 as a mask. Source/drain regions of the MOS transistor are formed by the lightly doped regions 105 and the heavily-doped regions 112.
Further, as shown in FIG. 4, a first metal silicide region 114 is formed on a surface of the source/drain regions by a metal-silicide process. A second metal silicide contact 115 region is also formed on a surface of the metal gate 103 by the metal-silicide process.
However, the MOS transistor formed by the existing process may have a relatively large parasite resistance (may refer as Rexternal in FIG. 4), and the relatively large parasitic resistance may affect performances of the MOS transistor. The disclosed device structures, methods and systems are directed to solve one or more problems set forth above and other problems.